The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a method for manufacturing a phase change memory device that simplifies a manufacturing procedure, thereby increasing a manufacturing yield and improving the characteristics of the phase change memory device.
Generally, memory devices can largely be categorized into a volatile RAM (random access memory) which loses inputted information when power is interrupted and a non-volatile ROM (read-only memory) which can continuously maintain the stored state of inputted information even when power is interrupted. Volatile RAM may include DRAM (dynamic RAM) and SRAM (static RAM) and non-volatile ROM may include a flash memory device such as an EEPROM (electrically erasable and programmable ROM).
It is well known that DRAM is an excellent memory device, however DRAM requires a high charge storing capacity and since the surface area of an electrode must be increased, it is difficult to accomplish a high level of integration. Further, flash memory stacks two gates on one another requiring a high operation voltage when compared to a source voltage. Accordingly, since a separate booster circuit is needed to form the necessary voltage for write and delete operations, it is difficult to obtain a high level of integration.
Research to develop a novel memory device having a simple configuration and capable of accomplishing a high level of integration while retaining the characteristics of non-volatile memory has been made. For example, a phase change memory device has recently been disclosed in the art.
In a phase change memory device, a phase change occurs in a phase change layer interposed between a lower electrode and an upper electrode. The phase change layer changes from a crystalline state to an amorphous state due to current flow between the lower electrode and the upper electrode. The information stored in a cell is determined by the medium difference in resistance between the crystalline state and the amorphous state.
In detail, in a phase change memory device, a chalcogenide layer being a compound layer made of germanium (Ge), stibium (Sb) and tellurium (Te) is employed as a phase change layer. As a current is applied, the phase change layer undergoes a phase change by heat, e.g. Joule heat, between the amorphous state and the crystalline state. Accordingly, in the phase change memory device, the specific resistance of the phase change layer in the amorphous state is higher than the specific resistance of the phase change layer in the crystalline state. In a read mode, sensing the current flowing through the phase change layer determines whether the information stored in a phase change cell has a logic value of ‘1’ or ‘0’.
In the phase change memory device, the conversion from a crystalline state to an amorphous state is called ‘reset’. Conversely, the conversion from an amorphous state to a crystalline state is called ‘set’. In terms of power consumption and operation speed, it is beneficial to utilize a low current for a reset and set (programming). Accordingly, by decreasing the contact area as much as possible between a phase change layer and a lower electrode, a current density can be increased and a required current can be decreased at an interface between two materials.
To achieve this in the conventional art, the lower electrode is formed in the shape of a plug in an effort to decrease the contact area between a lower electrode and a phase change layer.
Hereafter, a conventional phase change memory device will be schematically explained.
A first interlayer dielectric is formed on a semiconductor substrate having a gate line and source and drain regions. Contact plugs are formed in portions of the first interlayer dielectric corresponding to a region in which a phase change cell is to be formed and a region in which a line to be applied with a ground voltage (hereinafter, referred to as a “Vss line”) is to be formed such that the contact plugs respectively come into contact with the drain region and the source region.
An insulation layer is formed on the first interlayer dielectric including the contact plugs. A dot type pad is formed in the portion of the insulation layer that corresponds to the phase change cell forming region to contact the contact plug. A bar type Vss line is formed in the portion of the insulation layer that corresponds to the region having a ground voltage to contact the contact plug.
A second interlayer dielectric is formed on the insulation layer including the pad and the Vss line. A plug-shaped lower electrode is formed in the second interlayer dielectric to contact the pad. Further, a phase change layer and an upper electrode are sequentially formed on the lower electrode and on portions of the second interlayer dielectric adjacent to the lower electrode to form a phase change cell.
However, in the conventional art, the pad and the Vss line are formed through a damascene process. Manufacturing yield of the phase change memory device is decreased due to the damascene process being complicated and having a high processing cost.
Also, the characteristics of the phase change memory device can be deteriorated where the pad and the Vss line are formed as a tungsten layer through the damascene process because seams are likely to be formed in the tungsten layer.